In semiconductor processing, silicon-on-insulator (SOI) technology is becoming increasingly important since it permits the formation of high-speed integrated circuits. In SOI technology, an insulating material, e.g., a buried oxide, electrically isolates a top Si-containing layer from a bottom Si-containing substrate. The top Si-containing layer, which is oftentimes referred to in the art as the SOI layer, is generally the layer in which active devices such as transistors are formed. Devices formed using SOI technology offer many advantages over their bulk counterparts including, for example, higher performance, absence of latch-up, higher packing density and low voltage applications.
As SOI devices get smaller, the devices can suffer from a charge buildup in the body of the devices. This charge can cause a number of less than desirable effects including, for example, floating body effects. The floating body effects in SOI devices include a wide range of electrical behaviors resulting directly from the loss of control of the body charge state. Several examples of floating body effects are: (1) threshold voltage Vt that depends on the electrical history of the device (since the history of the device determines the body charge and effective back bias), (2) reduction of gate voltage control, (3) lowered snapback voltage, (4) degraded sub-Vt slope for static operation, (5) enhanced sub-Vt slope for dynamic operation, and (6) channel current overshoot. To ensure that specific devices do not suffer from these effects, a body contact is typically added as a method to drain off any charge in the body.
One known approach to provide body contacts is to cut out holes of the blanket buried oxide under the device's channel region so that the body in the device channel can be reached and biased thru the oxide opening. This approach provides a subtractive SOI substrate such as is shown, for example, in FIG. 1A. Specifically, FIG. 1A shows a metal oxide semiconductor field effect transistor (MOSFET) structure that includes a subtractive SOI substrate 10 having a patterned gate conductor 20 located atop a patterned gate dielectric 18. These patterned material layers are located atop the subtractive SOI substrate 10 that includes SOI channel region 16, source/drain regions 15, and buried oxide regions 14; the unlabeled region between the buried oxide regions 14 having boundaries defined by dotted lines represents the cut out buried oxide. The cut out oxide area serves as the body contact in the illustrated structure. Trench isolation region 12 is also shown in FIG. 1A.
Another approach is to start with the bulk technology and build a buried oxide underneath the Si source/drain. The intended buried oxide region is etched first and oxidized later. This approach provides an additive SOI substrate such as is shown, for example, in FIG. 1B. Specifically, FIG. 1B shows a MOSFET structure that includes an additive SOI substrate 11 having a patterned gate conductor 20 located atop a patterned gate dielectric 18. These patterned material layers are located atop the additive SOI substrate 11 that includes SOI channel region 16, source/drain regions 15, and buried oxide regions 14. Trench isolation region 12 is also shown in FIG. 1B. It is noted that in the structure shown in FIG. 1B the region between the buried oxide serves as the body contact of the field transistor device. Due to the processing of prior art additive SOI substrates, the Si plate tends to collapse during formation of the buried oxide.
In both SOI devices shown in FIGS. 1A and 1B, the active Si source/drain regions 15 are shielded from the Si substrate (not specifically shown) with a layer of buried oxide 14 underneath. A body contact is located beneath the channel region 16 and the underlying Si-containing substrate.
In actual IC designs, many source/drain regions are direct current (DC) nodes that do not switch at all. In particular, for the applied voltage VDD and ground GND regions buried oxides are actually undesirable. Moreover, the overall power bussing will miss the stabilization effects from the diffusion capacitance from the devices. For the individual circuits, the supply nodes will be bumped up and down more easily, and slow down the switching. Since the body contacts have to be at a distance away from the buried oxide, prior art layouts tend to be much larger than is necessary.